Matches for xilinx, 93 total results Sorted by newest | relevance
Wed Jun 17 17:52:39 UTC 2015 <assbot> Logged on 17-06-2015 17:32:11; ascii_field: (xilinx, altera, actel, etc. ~all~ make the bulk of their revenue by charging rent for 'properties' like 'the right to have a network card' in your fpga)
Wed Jun 17 17:32:11 UTC 2015 <ascii_field> (xilinx, altera, actel, etc. ~all~ make the bulk of their revenue by charging rent for 'properties' like 'the right to have a network card' in your fpga)
Wed Jun 17 15:51:00 UTC 2015 <assbot> Logged on 17-06-2015 13:17:59; asciilifeform: you can pick up a textbook and write a dram controller for fpga from first principles - and it won't work. because, for starters, only a small number of output cells in the chip can function on both rising and falling edge of clock cycle (what 'ddr' means) and only xilinx's closed turd knows where they are in the routing fabric;
Wed Jun 17 13:21:44 UTC 2015 <asciilifeform> the entire thing is cynically deliberate. notice how, e.g., xilinx boards, come with ethernet jack and magnetics? well, you can't actually ~use~ the ethernet without paying a per-unit license fee to the bastards
Wed Jun 17 13:17:59 UTC 2015 <asciilifeform> you can pick up a textbook and write a dram controller for fpga from first principles - and it won't work. because, for starters, only a small number of output cells in the chip can function on both rising and falling edge of clock cycle (what 'ddr' means) and only xilinx's closed turd knows where they are in the routing fabric;
Wed Jun 17 13:15:56 UTC 2015 <asciilifeform> http://log.bitcoin-assets.com/?date=17-06-2015#1165915 << key detail: 'IP-Core : MIG V:3.6.1'. that's 'memory interface generator', xilinx's gui turd. it shits out code which is a mere wrapper on a closed-source gigantic steaming pile of shit. and the output is unique to a particular model and subtype of chip.
Fri May 01 03:03:48 UTC 2015 <asciilifeform> mention of xilinx is especially on the point because a bit-flip in fpga routing fabric is catastrophic
Wed Apr 29 03:15:31 UTC 2015 <asciilifeform> i also have boxes that run closedsource linux crapolade (e.g., xilinx toolchain)
Sun Apr 12 04:52:54 UTC 2015 <asciilifeform> it had a xilinx spartan 1st ed. fpga inside. and was built like a tank.
Fri Apr 10 20:30:46 UTC 2015 <ascii_field> !s xilinx
Fri Apr 10 20:30:46 UTC 2015 <assbot> 62 results for 'xilinx' : http://s.b-a.link/?q=xilinx
Fri Apr 10 18:49:58 UTC 2015 <ascii_field> (before anyone spits back the old paper re: the fact of c-gates implemented on xilinx fabric - go and see how many of them you can fit. and how much room left for interconnects.)
Fri Apr 10 18:46:53 UTC 2015 <ascii_field> gabriel_laddel: to avoid rehashing ancient thread for a fifth time, stuck at the realization that reversing xilinx is futile.
Wed Apr 08 20:58:37 UTC 2015 <ascii_field> at one time there was much crowing re: a 'xilinx fpga backdoor'
Tue Mar 24 18:40:08 UTC 2015 <assbot> 56 results for 'xilinx' : http://s.b-a.link/?q=xilinx
Tue Mar 24 18:40:07 UTC 2015 <ascii_field> !s xilinx
Tue Mar 24 18:38:05 UTC 2015 <ascii_field> mats: neato, there was a similar project for xilinx 'virtex'
Wed Mar 11 21:30:20 UTC 2015 <ascii_field> trinque: you're talking about reverse-engineering, a la nvidia driver, xilinx (see old thread, etc.)
Thu Feb 05 01:49:29 UTC 2015 <asciilifeform> it's a little thing with a 'xilinx' fpga (nonvolatile) and 'ftdi' usb2 diddler
Sat Jan 03 17:34:34 UTC 2015 <mircea_popescu> asciilifeform: at the risk of repeating the last 100+ xilinx threads <<< basically, there was no torvalds for hardware. yet.